Methods for preventing fixed pattern programming

ABSTRACT

A method for preventing fixed pattern programming, the method including programming data into a pattern of memory cells in a memory array, and preventing fixed pattern programming by periodically scrambling the data so that the data is stored in a different pattern of memory cells in the memory array.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority from U.S. ProvisionalApplication Ser. No. 60/644,569, filed Jan. 19, 2005, which isincorporated herein by reference

FIELD OF THE INVENTION

The present invention relates generally to operating memory cells ofnon-volatile memory (NVM) arrays, such as programming and erasing, andparticularly to methods for preventing large differences in the programand erase history of cells, such as by data scrambling.

BACKGROUND OF THE INVENTION

Modern day non-volatile memory products incorporate the ability toelectrically program and erase the memory cells. In most cases, theerase operation is performed on a subset of cells and not individuallycell-by-cell, as normally performed during the programming operation.This means that erasure conditions are applied to the subset until thelast (slowest) cell finishes erasure, including verification that thecell has passed a predetermined level (erase verify).

Memory products incorporating tunneling enhanced hot hole injectionduring erasure, as in NROM (nitride read-only memory) technology,require high biasing of the transistor junction to create the injectedholes, through band-to-band tunneling, as may be seen in FIG. 1. Chargeinjection must be controlled to insure proper device operation, andaccordingly, step and verify algorithms are typically implemented. In atypical algorithm, charge is injected at a certain bias following by averify operation to ascertain whether the cell has reached itsdestination. If the destination has not been achieved, stronger chargeinjection is initiated via a higher bias and vice versa.

Reference is now made to FIG. 2, which illustrate a typical flow diagramof an erase algorithm of the prior art for NROM devices.

An erase pulse may be selected for erasing bits of the cells, comprisingselecting (“dialing in”) a negative gate voltage (Vg or Vcvpn—voltagefrom a charge pump) and a positive drain voltage (Vppd) (step 201) Theerase pulse may then be applied to the bits in a cell ensemble (step202). The threshold voltage Vt of the cells may be read with an eraseverify step (step 203) that checks if the memory cell threshold voltagehas been lowered to an erase verify (EV) voltage level or not.

If no cells have passed EV, then a new Vppd level may be set (dialed in)with a strong (i.e., large) increment (step 204). If some cells havepassed EV, then a new Vppd level may be set with a weak (i.e.,relatively smaller) increment (step 205). The process continues untilthe erase pulse has been applied to all cells. Each subgroup may receivean extra erase pulse at a higher level than the last pulse used to reachfull erasure for improving reliability. Application of additional pulsesis taught in various patent documents, such as U.S. Pat. No. 6,700,818and US Patent Applications 20050117395 and 20050058005, all assigned tothe present assignee of the present application, the disclosures ofwhich are incorporated herein by reference.

For tunneling enhanced hot hole injection, the process shown in FIG. 2usually has to be performed on both sides of the memory cell separately,resulting in longer erase time and lower performance

As the data stored in a subset of cells will most likely be random innature, some of the cells will be in the programmed state and some willbe in the erased state, prior to the erasure operation. Thus, if nospecial actions are taken, it is possible that a previously programmedcell upon which the erase operation is performed may reach a thresholdlevel near or at the erase verify level, while cells which were notprogrammed may become over-erased, wherein the threshold voltage issubstantially below the erase verify level. This may be seen in FIG. 3,which shows a prior art threshold voltage distribution of a subset ofcells in their native state, before any operation was performed, andafter erasure, where only a subgroup was previously programmed. Theerased cell distribution has two peaks. The higher peak is the thresholdvoltage distribution of the previously programmed cells, while the lowerpeak is that of the non-programmed cells, i.e., the cells that wereover-erased.

Several concerns arise from the over-erased situation. Over-erased cellsmay become leaky, i.e., conduct current without being biased to the “on”state (positive gate voltage for an n-MOSFET based memory cell)Over-erased cells may become hard to program, i.e., require excessivevoltages and time to bring them to the programmed state (above apredefined level, program verify level) A substantial difference in theoperating conditions (program and erase) may develop between cells whichhave been over-erased and cells which have not been over-erased. The sumof these effects may result in failure of the memory device, i.e., lossof data integrity.

Reference is now made to FIG. 4, which illustrates prior art thresholdvoltage distributions in a subgroup of cells in a memory array followingextensive cycling of a fixed pattern (10⁵ cycles) and a subsequentprogramming of a checkerboard pattern. A programming tail is shown tohave formed, due to the lack of sufficient over-erasure preventionmeasures

Prior art methods to prevent over-erasure of cell include partitioningof the erase subgroup, which has the advantage that smaller erasesubgroups insure better erase uniformity. However, disadvantages includeadditional overhead (reduced performance) and design complexity. Anotherprior art method involves programming before erasure, which ensures thatcells will not constantly go through erasure without ever beingprogrammed. However, this carries a substantial performance penalty intime and power.

Another prior art method involves programming after erasure, whichensures that cells will not be over-erased beyond a set level. However,this method also carries a substantial performance penalty in time andpower.

SUMMARY OF THE INVENTION

The present invention seeks to provide methods for preventing fixedpattern programming, which may prevent large differences in the programand erase history of cells of memory arrays, as is describedhereinbelow. The invention is described in detail hereinbelow withreference to memory cells of NVM arrays, and particularly to single bit,dual bit, multi-bit and multi-level NROM cells. However, it should beemphasized that the invention is not limited to NROM arrays.

There is thus provided in accordance with an embodiment of the inventiona method for preventing fixed pattern programming, the method includingprogramming data into a pattern of memory cells in a memory array, andpreventing fixed pattern programming by periodically scrambling the dataso that the data is stored in a different pattern of memory cells in thememory array.

The data may be scrambled by periodically inverting the data.Additionally or alternatively, the data may be scrambled by periodicallyrearranging a physical address of the data. Additionally oralternatively, the data may be scrambled by convolving the data with amixing pattern during programming and de-convolving the convolved dataduring a read operation. Additionally or alternatively, the data may bescrambled by periodically scrambling the data in accordance with aprogram and erase cycle counter. The data may be periodically scrambledrandomly or pseudo-randomly.

In accordance with a non-limiting embodiment of the invention, the datamay be scrambled as a function of a stored parameter inside the memoryarray. The stored parameter may be programmed in conjunction with thedata.

Additionally or alternatively, the data may be scrambled as a functionof a logical and/or physical address of the data.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood and appreciated more fully fromthe following detailed description taken in conjunction with theappended drawings in which:

FIG. 1 is a simplified graph of erasing NROM cells by tunneling enhancedhot hole injection in the prior art;

FIG. 2 is a simplified flow diagram of an erase algorithm of the priorart for NROM devices;

FIG. 3 is a simplified graph of a prior art threshold voltagedistribution of a subgroup of cells in a memory array in their nativestate and after erasure, wherein only a subset of the cells have beenpreviously programmed;

FIG. 4 is a simplified graph of prior art threshold voltagedistributions in a subgroup of cells in a memory array followingextensive cycling of a fixed pattern (10⁵ cycles) and a subsequentprogramming of a checkerboard pattern;

FIG. 5 is a simplified flow chart of the programming flow in a datascrambling implementation used to prevent fixed pattern programming, inaccordance with an embodiment of the invention; and

FIG. 6 is a simplified flow diagram of the read flow in the datascrambling implementation, in accordance with an embodiment of theinvention.

DETAILED DESCRIPTION OF EMBODIMENTS

Reference is now made to FIG. 5, which illustrates a method forpreventing fixed pattern programming in a non-volatile memory cellarray, in accordance with an embodiment of the present invention.Specifically, FIG. 5 is a simplified flow chart of the programming flowin a data scrambling implementation, as is now explained.

In accordance with an embodiment of the present invention, afterprogramming data into a pattern of memory cells in a memory array, fixedpattern programming is prevented by periodically scrambling the data sothat the data is stored in a different pattern of memory cells in thememory array (step 500). In a non-limiting embodiment of the presentinvention, the actual physical programmed data is forced to change fromcycle to cycle (step 501). Thus the rate at which systematic differencescan develop, due to fix pattern programming, may be substantiallyreduced. The actual data programmed into the cell array may be a resultof a manipulation of the input data by the user (step 502). Thismanipulation may change from cycle to cycle (step 503), or periodicallychange depending on a counter or a predefined threshold parameter (step504). Such a manipulation includes, but is not limited to, inverting theinput data, shifting it, transposing it, mixing the internal addressesof the bits, words, pages or any other data subset of the input data orof the erase subgroup, or convolving the input data with a changingmixing pattern. The changing mixing pattern may be from cycle to cycleor any other period, fixed, changing or random (step 505).

In accordance with a non-limiting embodiment of the present invention,wherein an erase sector consists of a group of pages (each programmedindividually), the input page data is convolved with a random orpseudo-random pattern determined by a counter and by the page locationinside the erase sector (step 506). As the counter changes from cycle tocycle, the actual data programmed to the page's physical address alsochanges (step 507). Moreover, since the random or pseudo-random patternis also determined by the page's location within the erase sector, theactual programmed data changes from page to page, even if the input datais the same for all pages (step 508). A counter used to scramble thedata and error detection parameters may be physically programmed in thesame flow (step 509). Error detection parameters are discussed, forexample, in U.S. patent application Ser. No. 10/695,457 (publicationnumber US 20040136236), the disclosure of which is incorporated hereinby reference, and corresponding PCT Application WO 2005/041108 “A MethodCircuit And System For Read Error Detection In A Non-Volatile MemoryArray”, both assigned to the present assignee of the present invention.The read error rate may be determined using a variety of error ratesampling and/or error detection techniques, for example, parity bit,checksum, CRC and various other techniques. Any error detection codingand/or evaluation technique, presently known or to be devised in thefuture, may be applicable to present invention.

Reference is now made to FIG. 6, which illustrates the read operationfor the data scrambling implementation of FIG. 5, in accordance with anembodiment of the invention. The data reliability is not affected by thescrambling scheme.

In one non-limiting embodiment, the page may be read, including theerror detection parameters (step 601). If a counter has been used, thealgorithm then evaluates the counter (step 602). The particular patternused may then be deconvolved (step 603) and the data extracted (step604).

Although the invention has been described in conjunction with specificembodiments thereof, it is evident that many alternatives, modificationsand variations will be apparent to those skilled in the art.Accordingly, it is intended to embrace all such alternatives,modifications and variations.

1. A method for preventing fixed pattern programming, the methodcomprising: programming data into a pattern of memory cells in a memoryarray; and preventing fixed pattern programming by periodicallyscrambling the data so that the data is stored in a different pattern ofmemory cells in the memory array.
 2. The method according to claim 1,wherein periodically scrambling the data comprises periodicallyinverting the data.
 3. The method according to claim 1, whereinperiodically scrambling the data comprises periodically rearranging aphysical address of said data.
 4. The method according to claim 1,wherein periodically scrambling the data comprises convolving said datawith a mixing pattern during programming and de-convolving the convolveddata during a read operation.
 5. The method according to claim 1,wherein periodically scrambling the data comprises periodicallyscrambling the data in accordance with a program and erase cyclecounter.
 6. The method according to claim 1, wherein the data isperiodically scrambled randomly.
 7. The method according to claim 1,wherein the data is periodically scrambled pseudo-randomly.
 8. Themethod according to claim 1, wherein periodically scrambling the datacomprises scrambling as a function of a stored parameter inside thememory array.
 9. The method according to claim 8, wherein said storedparameter is programmed in conjunction with said data
 10. The methodaccording to claim 1, wherein periodically scrambling the data comprisesscrambling as a function of a logical address of said data.
 11. Themethod according to claim 1, wherein periodically scrambling the datacomprises scrambling as a function of a physical address of said data.